1. Field of the Invention
The invention relates to debugging of advanced wafer-processing technologies, and specifically to quantifying the magnitude of and localizing defects on wafers.
2. Description of the Related Art
During the fabrication process, a wafer receives a number of doping, layering, and patterning steps. Each of these steps must meet exacting physical requirements. However, all steps have some variation from perfect calibration, thereby resulting in some variation on the wafer surface.
To minimize these variations, numerous inspections and tests are performed to detect undesirable defects. Once detected, these defects are analyzed in a process called failure analysis. During failure analysis, valuable information regarding problems with fabrication materials, process recipes, ambient air, personnel, process machines, and process materials can be discovered. Therefore, detection of defects on an integrated circuit is critical to high yields and process control.
When a new manufacturing process is being developed, a test structure may advantageously be manufactured specifically for testing the new manufacturing process. Alternatively, a wafer primarily including desired integrated circuit devices may also include test structures interspersed between the desired devices.
FIG. 1 illustrates two standard test structures 100: a fork 101 and a serpentine 102. To identify defects using one of these structures, a user would provide an input signal on one end of the structure and determine if an appropriate output signal was generated at the other end. These test structures can be placed on test chips or on actual production chips to test manufacturing processes.
Test structures 100 allow for the testing of xe2x80x9copensxe2x80x9d and xe2x80x9cshortsxe2x80x9d. An open is a failure in the connectivity or an excessively high resistance between two allegedly connected points. Serpentine 102 is typically used to detect opens. A short is a failure when connectivity exists between allegedly unconnected points. An open can be in a metal wire (line), a polysilicon line, a diffusion line, a contact, or a via. A short can be metal-to-metal, polysilicon-to-polysilicon, diffusion-to-diffusion, or contact-to-polysilicon. Fork 101 is typically used to detect shorts.
The above-referenced test structures, i.e. fork 101 and serpentine 102, have distinct drawbacks. For example, locating and analyzing failures using either structure is difficult and time consuming. Specifically, detecting an open or short condition tells the user nothing about exactly where on the fork or serpentine the defect is located.
Determining the location of the defect requires an inspection of the structure by the user. In the current art, visual inspection is a major method of determining chip failure. A visual inspection is a tedious process, which requires considerable time of an experienced product engineer. Moreover, to complicate matters, not all visual defects result in electrical failures. Therefore, to more closely analyze the visual defects, the user must typically perform both optical and scanning electron microscope (SEM) examinations. Furthermore, many defects are not visible by initial inspection, thereby making localization of the defects with a SEM extremely difficult if not impossible.
Of importance, even when defects are localized, current technology provides no means to quantify the magnitude of the defect. Both the location and the magnitude of the defect provide valuable information to the user for failure analysis and may even indicate the nature of the defect without performing failure analysis. Because of its expense and complexity, users try to minimize the use of failure analysis. As known by those skilled in the art, an extremely large defect is probably the result of particle contamination rather than incomplete etching. However, the identification of other types of defects is less clear. Therefore, even after localization, many types of defects must still be subjected to failure analysis.
Therefore, a need arises for a cost-effective method and test structure to quantify the magnitude of and localize defects on a wafer.
In accordance with the present invention, a test structure used for testing a manufacturing process provides defect information rapidly and accurately. The test structure is designed to mimic structures that will be present in a commercial device. The test structure includes a first plurality of lines provided in a first parallel orientation, a first decoder coupled to the first plurality of lines for selecting one of the first plurality of lines, and a first sense amplifier coupled to the output of the first decoder. To analyze an open, a line in the test structure is coupled to a sense amplifier. A high input signal is provided to the line. To determine the resistance of the open, a plurality of reference voltages are then provided to the sense amplifier.
In the present invention, a mathematical model of the resistance of the line based on the reference voltage provided to the sense amplifier is generated. In one embodiment, the mathematical model is generated using a simulation program such as HSPICE. Using this mathematical model, the test structure of the present invention can quickly detect defect levels down to a few defects-per-million locations tested at minimal expense.
The test structure can also determine the location of the defect(s) on the line. To achieve this, the test structure further includes a plurality of transistors, each transistor having a source, a drain, and a gate, the source and drain connected respectively to the selected line and an adjacent, non-selected line, and the gate coupled to selection circuitry. Using the selection circuitry, the transistors are selectively turned on/off, thereby creating predetermined paths through the test structure. The resistances associated with various paths are then compared to determine the location of the open(s). In this manner, the location of the open(s) can be determined within a few micrometers.
If the opens are substantially distributed across the tested line, then failure analysis can still be tedious, time-consuming, and sometimes non-conclusive. However, if one segment of the tested line has a significantly higher resistance than other segments, then failure analysis can be done quickly and yield much more certain conclusions. Thus, the present invention facilitates better failure analysis.
In accordance with the present invention, the test structure further includes a second plurality of lines provided in a second parallel orientation, a second decoder coupled to the second plurality of lines for selecting one of the second plurality of lines, and a second sense amplifier coupled to the output of the second decoder. In one embodiment, the second parallel orientation is perpendicular to the first parallel orientation. The first plurality of lines is formed from one layer and the second plurality of lines is formed from another layer in the integrated circuit. In this manner, separate feedback can be provided for each process layer.
To determine a short, a plurality of test strips are formed parallel to each of the first plurality of lines in the test structure. Each test strip is coupled to one of the second plurality of lines. By providing a high signal to the tested line in the first plurality of lines and monitoring the output signal of the appropriate one of the second plurality of lines, the present invention rapidly and accurately identifies a short between the tested line and the corresponding test strip.